1. Field of the Invention
The present invention relates to a resist which is used in the manufacture of an electronic device such as a thin film transistor and a manufacturing method of a display device which includes an active substrate having thin film transistors which are manufactured using the resist, wherein the present invention is particularly preferably suitable for simplifying manufacturing steps of the active substrate.
2. Description of the Related Arts
An active-matrix type display device, (or an active-matrix type driving-method image display device or simply referred to as a display device) which uses active elements such as thin film transistors as driving elements of pixels which are arranged in a matrix array has been popularly used. In this type of image display device, in many cases, a large number of pixel circuits and drive circuits which are constituted of active elements such as thin film transistors (TFT) or the like which are formed by using a silicon film as a semiconductor film are arranged on an insulating substrate thus displaying images of high quality.
FIG. 7 is a schematic cross-sectional view of an active substrate which explains a constitutional example of a thin film transistor. Here, the explanation is made by taking the thin film transistor of the pixel circuit as an example. The thin film transistor is formed as a non-metallic multi-layered film by stacking, on a main surface of a substrate 1 made of glass or the like, a gate electrode 2, a silicon nitride film 3 which constitutes an insulating layer referred to as a gate insulating film, an a-Si film 4 which constitutes an activation layer, and an n+ a-Si film 5 which is referred to as a contact layer in this order. The n+ a-Si film 5 is separated by way of a channel 16, wherein a source electrode (or a drain electrode) 61 is connected to one side of the n+ a-Si film 5 and a drain electrode (or a source electrode) 62 is connected to another side of the n+ a-Si film 5.
A protective insulating film (a passivation film, a PAS film) 14 is formed on the substrate 1 such that the protective insulating film 14 covers these electrodes 61, 62. Over the protective insulating film 14, a pixel electrode 15 which is connected to the source electrode (or the drain electrode) 61 via a contact hole formed in the protective insulating film 14 is formed. Here, the active substrate which forms a large number of such thin film transistors thereon is adhered to a color filter substrate which is also referred to as a counter substrate, and liquid crystal is sealed between the active substrate and the color filter substrate thus constituting a liquid crystal display device. Although an orientation film which imparts the initial orientation to molecules of the liquid crystal is formed on the pixel electrode 15, the orientation film is omitted from FIG. 7.
When the thin film transistor constitutes the pixel circuit of the liquid crystal display device, a display signal is supplied to the drain electrode 62 from a drain line (a signal line) not shown in the drawing. Due to the selection in response to a selection signal applied to the gate electrode 2 from a gate line (scanning line) not shown in the drawing, the thin film transistor becomes conductive and the pixel electrode 15 which is connected to the source electrode 61 is driven.
FIG. 8A to FIG. 8H are views for explaining essential steps of a conventional method for manufacturing a display device provided with the thin film transistor shown in FIG. 7. FIG. 8A to FIG. 8H show the manufacturing steps of the thin film transistor using so-called half-exposure processing. The manufacturing steps are explained in conjunction with FIG. 8A to FIG. 8H in order. First of all, a gate electrode 2 is formed on an insulating substrate (herein after referred to as a glass substrate) 1. On the surface of the glass substrate, a non-metallic multi-layered film is formed by stacking a silicon nitride (SiN) film 3 which constitutes an insulating layer, an a-Si film 4 which constitutes an active layer and an n+ a-Si film 5 which constitutes a contact layer in order such that these films cover the gate electrode 2. A metal film 6 which forms source and drain electrodes is stacked on the non-metallic multi-layered film. Then, a resist 7 is applied to the insulating substrate 1 such that the metal film 6 is covered with the resist 7 (FIG. 8A).
A so-called half-exposing mask is placed on the resist 7, the halftone exposure is applied to a portion of the resist corresponding to a channel portion of the thin film transistor and the normal exposure is applied to other portions of the resist and, thereafter, the developing is performed. Accordingly, as shown in FIG. 8B, it is possible to form a pattern having a cross-sectional shape in which a portion of the resist 7 indicated by an arrow b1 corresponding to the channel portion has a half film thickness.
When baking is applied to the above-mentioned structure, the resist is melted as shown in FIG. 8C and the resist pattern is collapsed and a profile of the channel portion becomes indefinite. Accordingly, wet etching is applied without performing the baking. As a result, end portions of the metal film 6 covered with the resist 7 are etched back as indicated by arrows d1, d2 (FIG. 8D).
Next, dry etching is applied to the n+ a-Si film 5 and the a-Si film 4 thus forming so-called islands. Here, as indicated by an arrow e1 in FIG. 8E, a film thickness of the resist 7 is also reduced largely (FIG. 8E). Thereafter, by applying oxygen ashing to the resist 7 thus largely reducing the thickness of the resist 7 as indicated by an arrow f1, a portion of the metal film 6 corresponding to the channel is exposed (FIG. 8F).
Then, by applying wet etching, the metal film 6 is divided into the portion constituting the source (or the drain) electrode and the portion constituting the drain (or the source) electrode (FIG. 8G). Here, a separated portion indicated by an arrow g1 and an outer end portion are also further etched back. Further, the n+ a-Si film 5 corresponding to the channel portion is removed by dry etching (FIG. 8H). Thereafter, the thin film transistor is formed through the steps explained in conjunction with FIG. 7. As documents which disclose a prior art relevant to such half exposure, Japanese Patent Laid-Open Hei 09/186233 (document 1) and Japanese Patent Laid-Open No. 324725/2001 (document 2) are named.
As described above, in the manufacturing steps of the display device which forms two kinds of resist patterns from one-layer resist using the half exposure processing, the baking is not performed due to the reason explained in conjunction with FIG. 8C and wet etching is performed and hence, it is impossible to obtain the sufficient adhesion of resist to the metal film. As a result, as shown in FIG. 8D and FIG. 8G, in addition to the formation of the excessive etching back (also referred to as side etching), an etchant is liable to easily intrude into an interface between the resist and the metal film and hence, the metal film is etched undesirably thus giving rise to the irregular shape, the reduction of film thickness and the film thickness irregularities.
On the other hand, Japanese Patent Laid-Open No. 26333/2002 (document 3) discloses a manufacturing method of an active matrix substrate in which patterning can be performed with high accuracy with the use of a two-layered resist which applies a resist having low sensitivity and low developing solubility as a lower layer and a resist having high sensitivity and high developing solubility as an upper layer.